FPGA Incremental Compilation—Divide and Conquer

For high-density, high-performance FPGA designs, the ability to iterate rapidly during design and debugging stages is critical to meet time-to-market demands. Today’s FPGA designers are encountering problems traditionally associated with ASIC designs, especially long place-and-route compilation times and difficulties achieving timing closure. To address these issues, FPGA and EDA vendors are beginning to offer incremental design and compilation capabilities previously available only with ASIC design tools. These capabilities include top-down methodologies that support evolving designs and engineering change orders (ECO), as well as bottom-up design methodologies including team-based design flows. Incremental compilation improves productivity by dramatically reducing design iteration times and preserving results to reach timing closure more easily.